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FPGAs are Field programmable Gate Arrays. They have a far higher density of
programmable gates than more conventional computing systems, but a lower clock
speed. They offer enormous potential for fine-grain parallel computing,
where the results of individual computations are almost immediately available
to other computing elements. This is quite unlike the coarse-grain parallel
computing used in modern supercomputers, where there are significant delays in
transferring data between different computing elements.
Quad-core PC chips are now widely available. A new generation of parallel
chips is under development where there may be as many as 64 parallel cores in a
closely coupled system. These devices are far less parallel than FPGAs but are
faster and may offer similar scope for fine-grain parallelism.
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Algorithms for fine-grain parallel computing were developed by a member of
SimCon in 1983 for the
Applied Dynamics International AD10 simulation computer.
This machine was by far the fastest real-time simulation system available in the mid
1980s, and was used in the design of Space Shuttle, comunications satellites, nuclear
powerplant, helicopters and a range of military hardware. The algorithms are applicable
to Fortran or C programming for FPGAs and multicore systems. Research is in progress in
collaboration with Liverpool Hope University and The University of Cape Town to apply
the algorithms to these devices.
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FPGAs are most efficiently programmed in fixed point arithmetic. Real numbers
are represented by scaled fractions. Each real value, x, is assigned a maximum absolute value,
scale(x), and is represented internally by an integer which is calculated as
X = 2**(n-1) * x / scale(x) where n is the number of bits used in the scaled fraction.
Usually, n would be 32 bits, but in an FPGA this is not necessarily the case.
The AD10 was also a fixed-point machine. A system was developed to maintain
the coefficients and data structures required to support the scaled-fraction
arithmetic. For example, where
a = b + c
and a, b and c have different scales,
a set of coefficients must be generated to correct the values so that the effective
calculation would be:
A = ( B + C * ( scale(c) / scale(b) ) ) * ( scale(b) / scale(a) )
where A, B and C are the scaled fractions
representing a, b and c.
This system will be applied in the FPGA programs.
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